The circuit depicted in FIG. 1 shows an exemplary fractional, oversampling based data recovery unit (DRU) 100. In this circuit (which receives at least one clock signal (CLK) 105), the phase generated by the digital voltage controlled oscillator (VCO), which is depicted as a numerically controlled oscillator (NCO) 110, is compared by a phase detector unit 120, at each clock cycle, with the phase of oversampled incoming data 130. The incoming data 130 is deserialized over N wires 140, as high speed DRUs typically operate in parallel. The phase error, which is filtered by a variable low pass filter (LPF) 150, is used to correct the frequency of the NCO 110, so that its phase tracks the phase of the incoming data. The sample selector (SS) 160 associates a numerical phase at each raw sample, and extracts the ones that are optimally located in an eye diagram. The SS 160 outputs at least one output data signal (DATAOUT) 190 and at least one enable signal (ENABLE) 195, which indicates which portions of output data signal 190 are the recovered data. The DRU bandwidth may be tuned by controlling the coefficients of the LPF 150.
In the illustrated example, the DRU 100 operates based on a negative feedback loop 180. In particular, the upper bound of the bandwidth at which the DRU 100 can be tuned to is limited by the amount of time (e.g., the processing time (PT) 170) it takes to calculate the control signal for the LPF 150 (e.g., signal “A”) from the NCO 110 phase (e.g., signal “C”) and the oversampled incoming data phase (e.g., signal “B”). This amount of processing time PT 170 increases as the datapath, which corresponds with the number N of wires, of the DRU 100 becomes wider. As integrated circuit technologies, such as the technology for field programmable gate arrays (FPGAs), continue to improve, DRU may be required to have wider datapath. As an example, it is common today to have a datapath width equal to 80 and above, and a clock frequency for the DRU in the fabric equal to about 150 MHz. In some cases, the PT may be in the range of 10 clock cycles or more. In some cases, the serdes speed and standard protocol speed may be increasing faster than the fabric speed.
Many protocols today, such as the Serial ATA (SATA), DisplayPort, Universal Serial Bus (USB) 3, etc., require a receiver with a wide bandwidth to be able to cope with the wide spread spectrum clock (SSC) level and the high sinusoidal jitter (SJ), which is in the range of few megahertz (MHz). DisplayPort, for example, has a challenging requirement of 2 MHz. Minimizing the PT in order to meet the wide jitter tolerance requirements of these protocols is a challenge today, and it will become more difficult going forward as technology continues to improve.